1. Field of the Invention
The present invention relates in general to an analog/digital converter, and more particularly to an algorithmic analog/digital converting circuit which is capable of reducing a layout area on chip and being operated regardless of an offset voltage from its operational amplifier.
2. Description of the Prior Art
Generally, an analog/digital converter may be representatively classified into an algorithmic analog/digital converting circuit and a digital signal processing circuit.
FIG. 1 is a schematic circuit diagram of an embodiment of a conventional algorithmic analog/digital converting circuit. As shown in the drawing, the conventional algorithmic analog/digital converting circuit comprises a plurality of switches SW1 to SW4 adapted for determining a flow of signal, a sample and hold circuit S/H adapted for sampling and holding a signal selected by said switches SW1 to SW4, an operational amplifier OP1 adapted for amplifying an output voltage signal from said sample and hold circuit S/H by double, a comparator CP1 adapted for comparing an output voltage signal from said operational amplifier OP1 with a reference voltage VR to output a control signal to said switches SW1 to SW4, an adder 1 responsive to said control signal from said comparator CP1 for outputting either said output voltage signal from said operational amplifier OP1 naturally or a resultant signal produced by subtracting said output voltage signal from said operational amplifier OP1 from said reference voltage VR to said sample and hold circuit S/H. The switches SW1 to SW4 each is composed of a MOS transistor.
Now, the operation of the conventional algorithmic analog/digital converting circuit constructed as above-mentioned will be described.
First, if the switch SW2 turns on, an input signal Vin is transferred through the switch SW2 to the sample and hold circuit S/H, which then samples and holds the signal Vin. Then, the operational amplifier OP1 amplifies the output voltage signal from the sample and hold circuit S/H by double and outputs the amplified voltage signal to an inverting input terminal of the comparator CP1, which then compares the amplified voltage signal from the operational amplifier OP1 with the reference voltage VR. Then, if the output voltage signal from the operational amplifier OP1 is not higher than the reference voltage VR, the comparator CP1 outputs a high voltage signal enabling the switch SW1 to turn on. If the output voltage signal from the operational amplifier OP1 is higher than the reference voltage VR, the comparator CP1 outputs a low voltage signal enabling the switch SW3 to turn on.
For this reason, as the switch SW1 or the switch SW3 turns on, the adder 1 outputs either the output voltage signal from the operational amplifier OP1 naturally or a resultant signal produced by subtracting the output voltage signal from the operational amplifier OP1 from the reference voltage VR to the sample and hold circuit S/H, which inputs the output voltage signal from the adder 1 when the switch SW2 in next sequence is turned on and then samples and holds the input signal. In order to achieve the analog/digital conversion, the operation as hereinbefore described is repeatedly performed.
Referring to FIG. 2 which is a detailed circuit diagram of an alternative embodiment of the conventional algorithmic analog/digital converting circuit, first, a condenser C1 is charged with an input signal Vin while a condenser C6 is charged with the offset voltage from an operational amplifier OP1 if switches SW2, SW4, SW5 and SW6 turn on.
Thereafter, if switches SW3 and SW5 turn on, the charge on the condenser C1 moves to a condenser C2 and the voltage sampled by the condenser C1 then appears at an output terminal of the operational amplifier OP1, which then charges a condenser C3 with the voltage sampled by the condenser C1.
When switches SW1 and SW4 are turned on, the voltage on the condenser C3 is transferred to a condenser C4 by an operational amplifier OP2 and the condenser C6 is charged with the same voltage as that on the condenser C4. At this time, the charged voltage on the condenser C2 is fully discharged, wherein a capacitance relationship between the used condensers C1 to C5 can be expressed as follows: EQU C1=C2=C3=C4-1/2C5
Thereafter, if the switches SW3 and SW5 turn on, the charged voltage on the condenser C5 transfers to the condenser C2, and at the same time the charged reference voltage VR on the condenser C1 transfers to the condenser C2. Therefore, in accordance with the capacitance relationship between the used condensers as above-mentioned, the operational amplifier OP1 outputs a resultant signal produced by subtracting the reference voltage VR from twice the original voltage sampled by the condenser C1 to a comparator CP1, which then converts the resultant signal into a signal which can be applied to a logic circuit. Then, the operation as hereinbefore described is repeatedly performed correspondingly to a predetermined number of bits.
In the conventional algorithmic analog/digital converting circuit, however, the three condensers C3, C4 and C5 and the operational amplifier OP2 must be used to amplify the sampled signal by double and the condenser C6 must be used to offset the offset voltage from the operational amplifier OP1. As the result, the algorithmic circuit is complex, thereby causing a layout area on chip to be larger.